The invention relates to a monolithic integrated memory circuit, constructed by means of enhancement transistors provided on a semiconductor substrate of a material of the group III-V, preferably Gallium Arsenide (GaAs), comprising a matrix of memory cells arranged in rows and columns, each memory cell of a column being connected to a first and a second bit line, which bit lines are coupled to a differential read amplifier circuit, said differential read amplifier circuit comprising two source-coupled field effect transistors, the coupled sources of which are controlled by a current source which itself is controlled by the output signal of an address decoder stage which enables the selection of the memory column, the drains of the coupled transistors providing a signal to the read bus of the memory.
A static random access memory comprising such a differential read amplifier circuit is known from the publication "Design of GaAs 1k bits static RAM" by MASAYUKI INO et al, IEEE Transactions on Electron Devices, Vol. ED-31, No. 9, September 1984 pages 1139-1144. This document describes a 1k bit static memory realized by means of gallium arsenide (GaAs) field effect transistors in direct coupled FET logic (DCFL) offering a low power consumption, high speed operation and a high integration density.
However, the gate-drain capacitance appearing during operation of the coupled transistors of this differential amplifier increases the rise time of the output signals collected on the read bus, thus increasing the memory access time and the transition time of the output signal.